1. Field of the Invention
This invention relates generally to differential input stages for operational amplifiers, and more particularly to techniques for controlling the transconductance of the input stage transistors when the amplifier's inputs are overdriven.
2. Description of the Related Art
Differential transistor pairs used as input stages for operational amplifiers can have their incremental or small signal transconductance (Gm) defined by their tail current. However, when a differential input voltage is such that the amplifier is overdriven, the difference current output by the pair transistors is limited to the tail current, and their Gm is essentially reduced to zero for large overdrives.
An alternative input scheme is shown in FIG. 1, which includes a first high Gm stage made from FETs 10, 12, 14 and 16, and a second Gm stage made from FETs 20, 22, 24 and 26. A resistor 27 having a resistance R is connected at one end to the common sources of FETs 14 and 16, and at its other end to the common sources of FETs 24 and 26. Bias currents are provided to the input stage by a current mirror 28 which includes FETs 30 and 32, which mirror fixed currents to FETs 12 and 22, respectively.
When connected as shown, FETs 14, 16, 24 and 26 form an input stage, and FETs 10, 12, 20 and 22 set the bias current of the input stage as dictated by the bias currents delivered via FETs 30 and 32. The output currents of FETs 14, 16, 24 and 26 are delivered to an output stage (not shown), which combines them so as to cancel the operating bias and deliver differences in current among the four FETs.
Assuming current mirror FETs 30 and 32 deliver equal currents to their respective complementary pairs (FETs 10,12 and FETs 20,22, respectively), the currents in all four of FETs 14, 16, 24, 26 should be the same, and the voltage across resistance R will be zero when the difference voltage applied to the ‘+’ and ‘−’ inputs is zero. A non-zero difference voltage applied to the ‘+’ and ‘−’ inputs will be translated, approximately, to the ends of resistor 27, and the resulting current will unbalance the currents in the four FETs 14, 16, 24 and 26. These four transistor currents can be differenced to result in a net output current which is proportional to the voltage across resistance R, such that R dominates the effective small signal transconductance of the input stage.
If the input is substantially overdriven, the input stage shown will continue to deliver larger and larger currents. For example, if ‘−’ is driven positive with respect to ‘+’, FET 14 will continue to drive R positive, even though the input level may be high enough to effectively turn off FET 16. At the same time, FET 26 will hold the other end of resistor 27 relatively low and sink the current from R. The resulting currents delivered from the drains of FETs 14 and 26 to the output stage mentioned above will continue to increase as the differential input voltage increases. These currents may not remain strictly proportional to the differential input signal, but they will cause the differential output current to increase beyond the standing bias level.
Conventionally, FETs 14, 16, 24 and 26 are strongly biased so that their individual Gms are large, such that the effective Gm of the input stage is dominated by resistance R. However, the initial transconductance values for the two high Gm stages need to be made much higher than the effective Gm in order for resistance R to dominate and define the small signal Gm. This requires a relatively high standing bias current. Further, if resistance R is made small, the differential Gm becomes a function of the properties of the FETs making up the high Gm stages, and of the bias currents, both of which are subject to manufacturing variability.